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en:verilog:start [2014/09/08 11:49]
alex created
en:verilog:start [2019/07/12 21:28] (current)
alex
Line 1: Line 1:
 ====== Verilog IP cores ====== ====== Verilog IP cores ======
  
 +  * [[.:axi:]]
 +  * [[.:axis:]]
   * [[.:​ethernet:​]]   * [[.:​ethernet:​]]
 +  * [[.:i2c:]]
 +  * [[.:​mersenne:​]]
 +  * [[.:pcie:]]
   * [[.:uart:]]   * [[.:uart:]]
   * [[.:​wishbone:​]]   * [[.:​wishbone:​]]
 +  * [[.:xfcp:]]