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en:verilog:start [2014/11/09 06:57] alexen:verilog:start [2019/07/12 19:28] (current) alex
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 ====== Verilog IP cores ====== ====== Verilog IP cores ======
  
 +  * [[.:axi:]]
   * [[.:axis:]]   * [[.:axis:]]
   * [[.:ethernet:]]   * [[.:ethernet:]]
 +  * [[.:i2c:]]
   * [[.:mersenne:]]   * [[.:mersenne:]]
 +  * [[.:pcie:]]
   * [[.:uart:]]   * [[.:uart:]]
   * [[.:wishbone:]]   * [[.:wishbone:]]
 +  * [[.:xfcp:]]