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en:verilog:uart:start [2014/09/09 05:03]
alex [Introduction]
en:verilog:uart:start [2014/11/09 08:27] (current)
alex [Introduction]
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 UART serial port with an AXI4-Stream interface. ​ Includes full MyHDL testbench with intelligent bus cosimulation endpoints. ​ Also includes example makefile-based project targeting a Xilinx Spartan 6 LX 45 on a Digilent Atlys board.  ​ UART serial port with an AXI4-Stream interface. ​ Includes full MyHDL testbench with intelligent bus cosimulation endpoints. ​ Also includes example makefile-based project targeting a Xilinx Spartan 6 LX 45 on a Digilent Atlys board.  ​
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 +===== Documentation =====
 +
 +[[readme]]
  
 ===== Repository ===== ===== Repository =====