Verilog Ethernet Stack

Ethernet stack with UDP/IP components in 8 bit and 64 bit AXI4-stream datapaths for 1G or 10G line rate processing. Includes LocalLink and Avalon bridges for use with all standard Xilinx and Altera tri-mode and 10G MACs. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.

Verilog Ethernet Components Readme

• Verilog Ethernet on GitHub

• Icarus Verilog simulator
• MyHDL