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| ====== Verilog Ethernet Stack ====== | ====== Verilog Ethernet Stack ====== | ||
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| + | ===== Introduction ===== | ||
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| + | Ethernet stack with UDP/IP components in 8 bit and 64 bit AXI4-stream datapaths for 1G or 10G line rate processing. Includes LocalLink and Avalon bridges for use with all standard Xilinx and Altera tri-mode and 10G MACs. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. | ||
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| + | ===== Documentation ===== | ||
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| + | [[readme]] | ||
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| + | ===== Repository ===== | ||
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| + | * [[https://github.com/alexforencich/verilog-ethernet|Verilog Ethernet on GitHub]] | ||
| + | ===== Links ===== | ||
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| + | * [[http://iverilog.icarus.com/|Icarus Verilog simulator]] | ||
| + | * [[http://www.myhdl.org/|MyHDL]] | ||