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--- en:verilog:uart:readme [2014/11/09 09:27]
alex [Signals and Parameters]
+++ en:verilog:uart:readme [2014/11/09 09:29]
alex [Signals and Parameters]
@@ Line 25: / Line 25: @@
       input wire clk - clock input
       input wire rst - reset input
-  * AXI Stream Interface (TX)
+    AXI Stream Interface (TX)
-    * ''input wire [DATA_WIDTH-1:0] input_axis_tdata'' - data input
+      input  wire [DATA_WIDTH-1:0] input_axis_tdata - data input
-    * ''input wire input_axis_tvalid'' - data valid input
+      input  wire input_axis_tvalid - data valid input
-    * ''output wire input_axis_tready'' - ready for data output
+      output wire input_axis_tready - ready for data output
-  * AXI Stream Interface (RX)
+    AXI Stream Interface (RX)
-    * ''output wire [DATA_WIDTH-1:0] output_axis_tdata'' - data output
+      output wire [DATA_WIDTH-1:0] output_axis_tdata - data output
-    * ''output wire output_axis_tvalid'' - data valid output
+      output wire output_axis_tvalid - data valid output
-    * ''input wire output_axis_tready'' - ready for data input
+      input  wire output_axis_tready - ready for data input
-  * UART Interface
+    UART Interface
-    * ''input wire rxd'' - UART RXD input
+      input  wire rxd - UART RXD input
-    * ''output wire txd'' - UART TXD output
+      output wire txd - UART TXD output
-  * Status
+    Status
-    * ''output wire tx_busy'' - operation in progress signal
+      output wire tx_busy - operation in progress signal
-    * ''output wire rx_busy'' - operation in progress signal
+      output wire rx_busy - operation in progress signal
-    * ''output wire rx_overrun_error'' - overrun error signal
+      output wire rx_overrun_error - overrun error signal
-    * ''output wire rx_frame_error'' - frame error signal
+      output wire rx_frame_error - frame error signal
-  * Configuration
+    Configuration
-    * ''input wire [15:0] prescale'' - BAUD rate prescale value
+      input wire [15:0] prescale - BAUD rate prescale value
 </code>