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--- en:verilog:uart:readme [2014/11/09 09:26]
alex [Source Files]
+++ en:verilog:uart:readme [2014/11/09 09:29]
alex [Signals and Parameters]
@@ Line 19: / Line 19: @@
 ==== Signals and Parameters ====
-  * Parameters
+<code>
-    * ''parameter DATA_WIDTH = 8'' - define width of data bus and transferred words in bits
+    Parameters
-  * Clock and reset
+      parameter DATA_WIDTH = 8 - define width of data bus and transferred words in bits
-    * ''input wire clk'' - clock input
+    Clock and reset
-    * ''input wire rst'' - reset input
+      input wire clk - clock input
-  * AXI Stream Interface (TX)
+      input wire rst - reset input
-    * ''input wire [DATA_WIDTH-1:0] input_axis_tdata'' - data input
+    AXI Stream Interface (TX)
-    * ''input wire input_axis_tvalid'' - data valid input
+      input  wire [DATA_WIDTH-1:0] input_axis_tdata - data input
-    * ''output wire input_axis_tready'' - ready for data output
+      input  wire input_axis_tvalid - data valid input
-  * AXI Stream Interface (RX)
+      output wire input_axis_tready - ready for data output
-    * ''output wire [DATA_WIDTH-1:0] output_axis_tdata'' - data output
+    AXI Stream Interface (RX)
-    * ''output wire output_axis_tvalid'' - data valid output
+      output wire [DATA_WIDTH-1:0] output_axis_tdata - data output
-    * ''input wire output_axis_tready'' - ready for data input
+      output wire output_axis_tvalid - data valid output
-  * UART Interface
+      input  wire output_axis_tready - ready for data input
-    * ''input wire rxd'' - UART RXD input
+    UART Interface
-    * ''output wire txd'' - UART TXD output
+      input  wire rxd - UART RXD input
-  * Status
+      output wire txd - UART TXD output
-    * ''output wire tx_busy'' - operation in progress signal
+    Status
-    * ''output wire rx_busy'' - operation in progress signal
+      output wire tx_busy - operation in progress signal
-    * ''output wire rx_overrun_error'' - overrun error signal
+      output wire rx_busy - operation in progress signal
-    * ''output wire rx_frame_error'' - frame error signal
+      output wire rx_overrun_error - overrun error signal
-  * Configuration
+      output wire rx_frame_error - frame error signal
-    * ''input wire [15:0] prescale'' - BAUD rate prescale value
+    Configuration
+      input wire [15:0] prescale - BAUD rate prescale value
+</code>
 ==== Description ====