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--- en:verilog:uart:readme [2014/11/09 08:36]
alex created
+++ en:verilog:uart:readme [2014/11/09 09:29]
alex [Signals and Parameters]
@@ Line 9: / Line 9: @@
 ==== Source Files ====
-  * rtl/uart.v - Wrapper for complete UART
+<code>
-  * rtl/uart_rx.v - UART receiver implementation
+    rtl/uart.v     : Wrapper for complete UART
-  * rtl/uart_tx.v - UART transmitter implementation
+    rtl/uart_rx.v  : UART receiver implementation
+    rtl/uart_tx.v  : UART transmitter implementation
+</code>
+===== uart module =====
+==== Signals and Parameters ====
+<code>
+    Parameters
+      parameter DATA_WIDTH = 8 - define width of data bus and transferred words in bits
+    Clock and reset
+      input wire clk - clock input
+      input wire rst - reset input
+    AXI Stream Interface (TX)
+      input  wire [DATA_WIDTH-1:0] input_axis_tdata - data input
+      input  wire input_axis_tvalid - data valid input
+      output wire input_axis_tready - ready for data output
+    AXI Stream Interface (RX)
+      output wire [DATA_WIDTH-1:0] output_axis_tdata - data output
+      output wire output_axis_tvalid - data valid output
+      input  wire output_axis_tready - ready for data input
+    UART Interface
+      input  wire rxd - UART RXD input
+      output wire txd - UART TXD output
+    Status
+      output wire tx_busy - operation in progress signal
+      output wire rx_busy - operation in progress signal
+      output wire rx_overrun_error - overrun error signal
+      output wire rx_frame_error - frame error signal
+    Configuration
+      input wire [15:0] prescale - BAUD rate prescale value
+</code>
+==== Description ====
+The ''uart'' module is simply a wrapper around the ''uart_rx'' and ''uart_tx'' modules.
+===== uart_rx module =====
+==== Signals and Parameters ====
+  * Parameters
+    * ''parameter DATA_WIDTH = 8'' - define width of data bus and transferred words in bits
+  * Clock and Reset
+    * ''input wire clk'' - clock input
+    * ''input wire rst'' - reset input
+  * AXI Stream Interface
+    * ''output wire [DATA_WIDTH-1:0] output_axis_tdata'' - data output
+    * ''output wire output_axis_tvalid'' - data valid output
+    * ''input wire output_axis_tready'' - ready for data input
+  * UART Interface
+    * ''input wire rxd'' - UART RXD input
+  * Status
+    * ''output wire busy'' - operation in progress signal
+    * ''output wire overrun_error'' - overrun error signal
+    * ''output wire frame_error'' - frame error signal
+  * Configuration
+    * ''input wire [15:0] prescale'' - BAUD rate prescale value
+==== Description ====
+The ''uart_rx'' module implements the UART receive function.  Bits received over the ''rxd'' pin are decoded and output on the AXI Stream interface.  The baud rate is determined by the ''prescale'' setting, which should be set to Fclk / (baud * 8).  ''prescale'' is a port and not a parameter so it can be changed at run time if necessary.  The ''uart_rx'' module also generates frame and overrun error signals.  The ''frame_error'' signal indicates that the stop bit was not received correctly, while the ''overrun_error'' signal indicates that a byte was received before the previous one was read, causing the older data byte to be overwritten.
+===== uart_tx module =====
+==== Signals and Parameters ====
+  * Parameters
+    * ''parameter DATA_WIDTH = 8'' - define width of data bus and transferred words in bits
+  * Clock and Reset
+    * ''input wire clk'' - clock input
+    * ''input wire rst'' - reset input
+  * AXI Stream Interface
+    * ''input wire [DATA_WIDTH-1:0] input_axis_tdata'' - data input
+    * ''input wire input_axis_tvalid'' - data valid input
+    * ''output wire input_axis_tready'' - ready for data output
+  * UART Interface
+    * ''output wire txd'' - UART TXD output
+  * Status
+    * ''output wire busy'' - operation in progress signal
+  * Configuration
+    * ''input wire [15:0] prescale'' - BAUD rate prescale value
-==== AXI interface ====
+===== AXI interface =====
 The main interface to the user design is an AXI4-Stream interface that consists of the tdata, tvalid, and tready signals.  tready flows in the opposite direction.  tdata is considered valid when tvalid is high.  The destination will accept data only when tready is high.  Data is transferred from the source to the destination only when both tvalid and tready are high, otherwise the bus is stalled.
-=== AXI Stream Interface Example ===
+==== AXI Stream Interface Example ====
 two byte transfer with sink pause after each byte
@@ Line 29: / Line 111: @@
            ______________             _____             ___________
     tready               \___________/     \___________/
 </code>
@@ Line 37: / Line 120: @@
 ==== Testbench Files ====
-  * tb/axis_ep.py - MyHDL AXI Stream endpoints
+  * ''tb/axis_ep.py'' - MyHDL AXI Stream endpoints
-  * tb/test_uart_rx.py - MyHDL testbench for uart_rx module
+  * ''tb/test_uart_rx.py'' - MyHDL testbench for uart_rx module
-  * tb/test_uart_rx.v - Verilog toplevel file for uart_rx cosimulation
+  * ''tb/test_uart_rx.v'' - Verilog toplevel file for uart_rx cosimulation
-  * tb/test_uart_tx.py - MyHDL testbench for uart_tx module
+  * ''tb/test_uart_tx.py'' - MyHDL testbench for uart_tx module
-  * tb/test_uart_tx.v - Verilog toplevel file for uart_tx cosimulation
+  * ''tb/test_uart_tx.v'' - Verilog toplevel file for uart_tx cosimulation
-  * tb/uart_ep.py - MyHDL UART endpoints
+  * ''tb/uart_ep.py'' - MyHDL UART endpoints
 ===== Example Design =====