https://alexforencich.com/wiki/ 2026-04-14T08:37:25+00:00 https://alexforencich.com/wiki/ https://alexforencich.com/wiki/_media/wiki/dokuwiki.svg text/html 2019-04-04T04:58:31+00:00 Anonymous (anonymous@undisclosed.example.com) https://alexforencich.com/wiki/en/verilog/xfcp/readme?rev=1554353911&do=diff Extensible FPGA Control Platform For more information and updates: <http://alexforencich.com/wiki/en/verilog/xfcp/start> GitHub repository: <https://github.com/alexforencich/xfcp> Introduction The Extensible FPGA control platform (XFCP) is a framework that enables simple interfacing between an FPGA design in verilog and control software. XFCP uses a source-routed packet switched bus over AXI stream to interconnect components in an FPGA design, eliminating the need to assign and manage addre… text/html 2019-04-04T05:22:55+00:00 Anonymous (anonymous@undisclosed.example.com) https://alexforencich.com/wiki/en/verilog/xfcp/start?rev=1554355375&do=diff Extensible FPGA Control Platform Introduction The Extensible FPGA control platform (XFCP) is a framework that enables simple interfacing between an FPGA design in verilog and control software. XFCP uses a source-routed packet switched bus over AXI stream to interconnect components in an FPGA design, eliminating the need to assign and manage addresses, enabling simple bus enumeration, and vastly reducing dependencies between the FPGA design and the control software. XFCP currently supports op…