Alex Forencich - en:verilog:uart https://alexforencich.com/wiki/ 2026-05-05T09:20:07+00:00 Alex Forencich https://alexforencich.com/wiki/ https://alexforencich.com/wiki/_media/wiki/dokuwiki.svg text/html 2014-11-09T08:39:42+00:00 Anonymous (anonymous@undisclosed.example.com) Verilog UART Readme https://alexforencich.com/wiki/en/verilog/uart/readme?rev=1415522382&do=diff Verilog UART Readme Introduction This is a basic UART to AXI Stream IP core, written in Verilog with MyHDL testbenches. Documentation The main code for the core exists in the rtl subdirectory. The uart_rx.v and uart_tx.v files are the actual implementation, uart.v simply instantiates both modules and makes a couple of internal connections. text/html 2014-11-09T07:27:12+00:00 Anonymous (anonymous@undisclosed.example.com) Verilog UART https://alexforencich.com/wiki/en/verilog/uart/start?rev=1415518032&do=diff Verilog UART Introduction UART serial port with an AXI4-Stream interface. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. Also includes example makefile-based project targeting a Xilinx Spartan 6 LX 45 on a Digilent Atlys board.