Alex Forencich - en:verilog:mersenne https://alexforencich.com/wiki/ 2026-05-13T12:55:08+00:00 Alex Forencich https://alexforencich.com/wiki/ https://alexforencich.com/wiki/_media/wiki/dokuwiki.svg text/html 2014-11-09T09:05:10+00:00 Anonymous (anonymous@undisclosed.example.com) Verilog Mersenne Twister Readme https://alexforencich.com/wiki/en/verilog/mersenne/readme?rev=1415523910&do=diff Verilog Mersenne Twister Readme Introduction This is an implementation of the Mersenne Twister pseudorandom number generator, written in Verilog with MyHDL testbenches. Documentation The main code exists in the rtl subdirectory. The 32 bit and 64 bit implementations are contained entirely in the files axis_mt19937.v and axis_mt19937_64.v, respectively. The axis_mt19937 implements the 32-bit mt19937ar algorithm while the axis_mt19937_64 module implements the 64-bit mt19937-64 algorithm. Th… text/html 2014-11-09T09:01:53+00:00 Anonymous (anonymous@undisclosed.example.com) Verilog Mersenne Twister PRNG https://alexforencich.com/wiki/en/verilog/mersenne/start?rev=1415523713&do=diff Verilog Mersenne Twister PRNG Introduction Mersenne Twister PRNG with an AXI4-Stream interface. Data can be read out on every cycle after seeding completes, resulting in 5.6 Gbps for the 32 bit version and 11.2 Gbps for the 64 bit version when running at 175