Alex Forencich - en:verilog:i2c https://alexforencich.com/wiki/ 2026-05-14T02:27:13+00:00 Alex Forencich https://alexforencich.com/wiki/ https://alexforencich.com/wiki/_media/wiki/dokuwiki.svg text/html 2019-05-28T08:24:44+00:00 Anonymous (anonymous@undisclosed.example.com) Verilog I2C interface https://alexforencich.com/wiki/en/verilog/i2c/readme?rev=1559031884&do=diff Verilog I2C interface For more information and updates: <http://alexforencich.com/wiki/en/verilog/i2c/start> GitHub repository: <https://github.com/alexforencich/verilog-i2c> Introduction I2C interface components. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. Documentation i2c_init module Template module for peripheral initialization via I2C. For use when one or more peripheral devices (i.e. PLL chips, jitter attenuators, clock muxes, etc.) need to be initia… text/html 2019-05-28T08:21:21+00:00 Anonymous (anonymous@undisclosed.example.com) Verilog UART https://alexforencich.com/wiki/en/verilog/i2c/start?rev=1559031681&do=diff Verilog UART Introduction I2C interface components. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. Documentation Verilog I2C interface Repository Verilog I2C on GitHub Links Icarus Verilog simulatorMyHDL