Alex Forencich - en:verilog:ethernet https://alexforencich.com/wiki/ 2026-04-11T21:07:09+00:00 Alex Forencich https://alexforencich.com/wiki/ https://alexforencich.com/wiki/_media/wiki/dokuwiki.svg text/html 2019-04-04T05:34:16+00:00 Anonymous (anonymous@undisclosed.example.com) Verilog Ethernet Components Readme https://alexforencich.com/wiki/en/verilog/ethernet/readme?rev=1554356056&do=diff Verilog Ethernet Components Readme For more information and updates: <http://alexforencich.com/wiki/en/verilog/ethernet/start> GitHub repository: <https://github.com/alexforencich/verilog-ethernet> Introduction Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit … text/html 2019-07-12T19:29:04+00:00 Anonymous (anonymous@undisclosed.example.com) Verilog Ethernet Components https://alexforencich.com/wiki/en/verilog/ethernet/start?rev=1562959744&do=diff Verilog Ethernet Components Introduction Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G, a 10G PCS/PMA PHY module, and a 10G combination MAC/PCS/PMA module. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.