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en:verilog:wishbone:start [2014/09/08 11:56]
alex
en:verilog:wishbone:start [2015/01/25 08:58] (current)
alex [Introduction]
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 ====== Verilog Wishbone components ====== ====== Verilog Wishbone components ======
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 +===== Introduction =====
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 +Collection of Wishbone bus components. ​ Most components are fully parametrizable in interface widths. ​ Includes full MyHDL testbench with intelligent bus cosimulation endpoints.
  
 ===== Repository ===== ===== Repository =====