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en:verilog:wishbone:start [2014/09/10 06:35] – [Verilog Wishbone components] alexen:verilog:wishbone:start [2015/01/25 07:58] (current) – [Introduction] alex
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 ===== Introduction ===== ===== Introduction =====
  
-Collection of wishbone bus components, written in Verilog.  Does not yet support MyHDL.  +Collection of Wishbone bus components.  Most components are fully parametrizable in interface widths.  Includes full MyHDL testbench with intelligent bus cosimulation endpoints.
  
 ===== Repository ===== ===== Repository =====
en/verilog/wishbone/start.1410330936.txt.gz · Last modified: by alex
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