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--- en:verilog:wishbone:start [2014/09/08 09:50] – created alex
+++ en:verilog:wishbone:start [2015/01/25 07:58] (current) – [Introduction] alex
@@ Line 1: / Line 1: @@
 ====== Verilog Wishbone components ======
+===== Introduction =====
+Collection of Wishbone bus components.  Most components are fully parametrizable in interface widths.  Includes full MyHDL testbench with intelligent bus cosimulation endpoints.
+===== Repository =====
+  * [[http://github.com/alexforencich/verilog-wishbone/|Verilog Wishbone on GitHub]]
+===== Links =====
+  * [[http://opencores.org/opencores,wishbone|Wishbone bus]]
+  * [[http://iverilog.icarus.com/|Icarus Verilog simulator]]
+  * [[http://www.myhdl.org/|MyHDL]]