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en:verilog:wishbone:start [2014/09/08 11:56] alex |
en:verilog:wishbone:start [2014/09/10 08:35] alex [Verilog Wishbone components] |
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| ====== Verilog Wishbone components ====== | ====== Verilog Wishbone components ====== | ||
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| + | ===== Introduction ===== | ||
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| + | Collection of wishbone bus components, written in Verilog. Does not yet support MyHDL. | ||
| ===== Repository ===== | ===== Repository ===== | ||