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en:verilog:uart:start [2014/09/09 03:03] – alexen:verilog:uart:start [2014/11/09 07:27] (current) – [Introduction] alex
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 ===== Introduction ===== ===== Introduction =====
  
-A UART serial port with an AXI4-Stream interface.  Includes full MyHDL testbench with intelligent bus cosimulation endpoints.  Also includes example makefile-based project targeting a Xilinx Spartan 6 LX 45 on a Digilent Atlys board.  +UART serial port with an AXI4-Stream interface.  Includes full MyHDL testbench with intelligent bus cosimulation endpoints.  Also includes example makefile-based project targeting a Xilinx Spartan 6 LX 45 on a Digilent Atlys board.   
 + 
 +===== Documentation ===== 
 + 
 +[[readme]]
  
 ===== Repository ===== ===== Repository =====
en/verilog/uart/start.1410231811.txt.gz · Last modified: by alex
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