Differences

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--- en:verilog:uart:start [2014/09/08 09:50] – created alex
+++ en:verilog:uart:start [2014/11/09 07:27] (current) – [Introduction] alex
@@ Line 1: / Line 1: @@
 ====== Verilog UART ======
+===== Introduction =====
+UART serial port with an AXI4-Stream interface.  Includes full MyHDL testbench with intelligent bus cosimulation endpoints.  Also includes example makefile-based project targeting a Xilinx Spartan 6 LX 45 on a Digilent Atlys board.
+===== Documentation =====
+[[readme]]
+===== Repository =====
+  * [[http://github.com/alexforencich/verilog-uart/|Verilog UART on GitHub]]
+===== Links =====
+  * [[http://iverilog.icarus.com/|Icarus Verilog simulator]]
+  * [[http://www.myhdl.org/|MyHDL]]