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en:verilog:start [2014/09/17 03:12]
alex
en:verilog:start [2019/05/28 10:20]
alex
Line 1: Line 1:
 ====== Verilog IP cores ====== ====== Verilog IP cores ======
  
 +  * [[.:axi:]]
 +  * [[.:axis:]]
   * [[.:​ethernet:​]]   * [[.:​ethernet:​]]
 +  * [[.:i2c:]]
   * [[.:​mersenne:​]]   * [[.:​mersenne:​]]
   * [[.:uart:]]   * [[.:uart:]]
   * [[.:​wishbone:​]]   * [[.:​wishbone:​]]
 +  * [[.:xfcp:]]