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--- en:verilog:i2c:readme [2019/05/28 08:23] – created alex
+++ en:verilog:i2c:readme [2019/05/28 08:24] (current) – [Source Files] alex
@@ Line 47: / Line 47: @@
 I2C slave module with parametrizable Wishbone master interface.
-===== Source Files =====
+==== Source Files ====
     axis_fifo.v             : AXI stream FIFO