This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
en:verilog:ethernet:start [2014/09/09 04:48]
alex [Verilog Ethernet Stack]
en:verilog:ethernet:start [2019/07/12 21:29] (current)
Line 1: Line 1:
-====== Verilog Ethernet ​Stack ======+====== Verilog Ethernet ​Components ​======
 ===== Introduction ===== ===== Introduction =====
-Ethernet ​stack with UDP/​IP ​components ​in 8 bit and 64 bit datapaths for up to 10G line rate processing Includes full MyHDL testbench with intelligent bus cosimulation endpoints. ​ +Collection of Ethernet-related ​components ​for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). Includes modules ​for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes ​MAC modules for gigabit and 10G, a 10G PCS/PMA PHY module, and a 10G combination MAC/PCS/PMA module. Also includes ​full MyHDL testbench with intelligent bus cosimulation endpoints.
 +===== Documentation =====
 +===== Repository =====
 +  * [[https://​github.com/​alexforencich/​verilog-ethernet|Verilog Ethernet on GitHub]]
 ===== Links ===== ===== Links =====