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| - | ====== Verilog Ethernet Stack ====== | + | ====== Verilog Ethernet Components ====== |
| ===== Introduction ===== | ===== Introduction ===== | ||
| - | Ethernet stack with UDP/IP components in 8 bit and 64 bit AXI4-stream datapaths for 1G or 10G line rate processing. Includes LocalLink and Avalon bridges for use with all standard Xilinx and Altera MACs. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. | + | Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G, a 10G PCS/PMA PHY module, and a 10G combination MAC/PCS/PMA module. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints. |
| + | ===== Documentation ===== | ||
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| + | [[readme]] | ||
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| + | ===== Repository ===== | ||
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| + | * [[https://github.com/alexforencich/verilog-ethernet|Verilog Ethernet on GitHub]] | ||
| ===== Links ===== | ===== Links ===== | ||