Differences

This shows you the differences between two versions of the page.

--- en:verilog:ethernet:start [2014/09/09 04:48]
alex [Verilog Ethernet Stack]
+++ en:verilog:ethernet:start [2019/04/04 07:23]
alex [Verilog Ethernet Stack]
@@ Line 1: / Line 1: @@
-====== Verilog Ethernet Stack ======
+====== Verilog Ethernet Components ======
 ===== Introduction =====
-Ethernet stack with UDP/IP components in 8 bit and 64 bit datapaths for up to 10G line rate processing.  Includes full MyHDL testbench with intelligent bus cosimulation endpoints.
+Ethernet stack with UDP/IP components in 8 bit and 64 bit AXI4-stream datapaths for 1G or 10G line rate processing.  Includes LocalLink and Avalon bridges for use with all standard Xilinx and Altera tri-mode and 10G MACs.  Includes full MyHDL testbench with intelligent bus cosimulation endpoints.
+===== Documentation =====
+[[readme]]
+===== Repository =====
+  * [[https://github.com/alexforencich/verilog-ethernet|Verilog Ethernet on GitHub]]
 ===== Links =====