| Both sides previous revisionPrevious revision | |
| en:verilog:ethernet:readme [2019/04/04 05:28] – alex | en:verilog:ethernet:readme [2019/04/04 05:34] (current) – alex |
|---|
| 10G Ethernet MAC with XGMII interface and FIFOs. Datapath selectable between | 10G Ethernet MAC with XGMII interface and FIFOs. Datapath selectable between |
| 32 and 64 bits. | 32 and 64 bits. |
| | |
| | ==== eth_mac_mii module ==== |
| | |
| | Ethernet MAC with MII interface. |
| | |
| | ==== eth_mac_mii_fifo module ==== |
| | |
| | Ethernet MAC with MII interface and FIFOs. |
| |
| ==== eth_mac_phy_10g module ==== | ==== eth_mac_phy_10g module ==== |
| |
| Fully parametrizable combinatorial parallel LFSR/CRC module. | Fully parametrizable combinatorial parallel LFSR/CRC module. |
| | |
| | ==== mii_phy_if module ==== |
| | |
| | MII PHY interface and clocking logic. |
| |
| ==== rgmii_phy_if module ==== | ==== rgmii_phy_if module ==== |
| rtl/eth_axis_tx_64.v : Ethernet frame transmitter (64 bit) | rtl/eth_axis_tx_64.v : Ethernet frame transmitter (64 bit) |
| rtl/eth_demux.v : Ethernet frame demultiplexer | rtl/eth_demux.v : Ethernet frame demultiplexer |
| rtl/eth_mac_1g.v : Gigabit Etherent GMII MAC | rtl/eth_mac_1g.v : Gigabit Ethernet GMII MAC |
| rtl/eth_mac_1g_fifo.v : Gigabit Etherent GMII MAC with FIFO | rtl/eth_mac_1g_fifo.v : Gigabit Ethernet GMII MAC with FIFO |
| rtl/eth_mac_1g_gmii.v : Tri-mode Ethernet GMII/MII MAC | rtl/eth_mac_1g_gmii.v : Tri-mode Ethernet GMII/MII MAC |
| rtl/eth_mac_1g_gmii_fifo.v : Tri-mode Ethernet GMII/MII MAC with FIFO | rtl/eth_mac_1g_gmii_fifo.v : Tri-mode Ethernet GMII/MII MAC with FIFO |
| rtl/eth_mac_1g_rgmii.v : Tri-mode Ethernet RGMII MAC | rtl/eth_mac_1g_rgmii.v : Tri-mode Ethernet RGMII MAC |
| rtl/eth_mac_1g_rgmii_fifo.v : Tri-mode Ethernet RGMII MAC with FIFO | rtl/eth_mac_1g_rgmii_fifo.v : Tri-mode Ethernet RGMII MAC with FIFO |
| rtl/eth_mac_10g.v : 10G Etherent XGMII MAC | rtl/eth_mac_10g.v : 10G Ethernet XGMII MAC |
| rtl/eth_mac_10g_fifo.v : 10G Etherent XGMII MAC with FIFO | rtl/eth_mac_10g_fifo.v : 10G Ethernet XGMII MAC with FIFO |
| rtl/eth_mac_phy_10g.v : 10G Etherent XGMII MAC/PHY | rtl/eth_mac_mii.v : Ethernet MII MAC |
| rtl/eth_mac_phy_10g_fifo.v : 10G Etherent XGMII MAC/PHY with FIFO | rtl/eth_mac_mii_fifo.v : Ethernet MII MAC with FIFO |
| rtl/eth_mac_phy_10g_rx.v : 10G Etherent XGMII MAC/PHY RX with FIFO | rtl/eth_mac_phy_10g.v : 10G Ethernet XGMII MAC/PHY |
| rtl/eth_mac_phy_10g_tx.v : 10G Etherent XGMII MAC/PHY TX with FIFO | rtl/eth_mac_phy_10g_fifo.v : 10G Ethernet XGMII MAC/PHY with FIFO |
| | rtl/eth_mac_phy_10g_rx.v : 10G Ethernet XGMII MAC/PHY RX with FIFO |
| | rtl/eth_mac_phy_10g_tx.v : 10G Ethernet XGMII MAC/PHY TX with FIFO |
| rtl/eth_mux.v : Ethernet frame multiplexer | rtl/eth_mux.v : Ethernet frame multiplexer |
| rtl/gmii_phy_if.v : GMII PHY interface | rtl/gmii_phy_if.v : GMII PHY interface |
| rtl/lfsr.v : Generic LFSR/CRC module | rtl/lfsr.v : Generic LFSR/CRC module |
| rtl/oddr.v : Generic DDR output register | rtl/oddr.v : Generic DDR output register |
| | rtl/mii_phy_if.v : MII PHY interface |
| rtl/rgmii_phy_if.v : RGMII PHY interface | rtl/rgmii_phy_if.v : RGMII PHY interface |
| rtl/ssio_ddr_in.v : Generic source synchronous IO DDR input module | rtl/ssio_ddr_in.v : Generic source synchronous IO DDR input module |