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en:verilog:axis:start [2014/11/09 08:03] alex created |
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| Collection of AXI Stream bus components. Most components are fully parametrizable in interface widths. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. | Collection of AXI Stream bus components. Most components are fully parametrizable in interface widths. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. | ||
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| + | * AXI stream bus with adapter | ||
| + | * AXI stream synchronous FIFO | ||
| + | * AXI stream asynchronous FIFO | ||
| + | * AXI stream synchronous frame FIFO | ||
| + | * AXI stream asynchronous frame FIFO | ||
| + | * AXI stream/LocalLink bridge | ||
| + | * AXI stream rate limiter | ||
| + | * AXI stream statistics collection | ||
| + | |||
| + | ===== Documentation ===== | ||
| + | |||
| + | [[readme]] | ||
| + | |||
| ===== Repository ===== | ===== Repository ===== | ||