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en:verilog:wishbone:start [2014/09/10 08:35] alex [Verilog Wishbone components] |
en:verilog:wishbone:start [2015/01/25 08:58] (current) alex [Introduction] |
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| ===== Introduction ===== | ===== Introduction ===== | ||
| - | Collection of wishbone bus components, written in Verilog. Does not yet support MyHDL. | + | Collection of Wishbone bus components. Most components are fully parametrizable in interface widths. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. |
| ===== Repository ===== | ===== Repository ===== | ||