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en:verilog:wishbone:start [2014/09/08 11:50] alex created |
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| ====== Verilog Wishbone components ====== | ====== Verilog Wishbone components ====== | ||
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| + | ===== Introduction ===== | ||
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| + | Collection of Wishbone bus components. Most components are fully parametrizable in interface widths. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. | ||
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| + | ===== Repository ===== | ||
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| + | * [[http://github.com/alexforencich/verilog-wishbone/|Verilog Wishbone on GitHub]] | ||
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| + | ===== Links ===== | ||
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| + | * [[http://opencores.org/opencores,wishbone|Wishbone bus]] | ||
| + | * [[http://iverilog.icarus.com/|Icarus Verilog simulator]] | ||
| + | * [[http://www.myhdl.org/|MyHDL]] | ||