Verilog UART

UART serial port with an AXI4-Stream interface. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. Also includes example makefile-based project targeting a Xilinx Spartan 6 LX 45 on a Digilent Atlys board.

• Verilog UART on GitHub

• Icarus Verilog simulator
• MyHDL