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en:verilog:uart:readme [2014/11/09 09:39] alex |
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| Both interfaces also present a 'busy' signal that is high when an operation is taking place. The receiver also presents overrun error and frame error strobe outputs. If the data word currently in the tdata output register is not read before another word is received, then a single cycle pulse will be emitted from overrun_error and the word is discarded. If the receiver does not get a stop bit of the right level, then a single pulse will be emitted from the frame_error output and the received word will be discarded. | Both interfaces also present a 'busy' signal that is high when an operation is taking place. The receiver also presents overrun error and frame error strobe outputs. If the data word currently in the tdata output register is not read before another word is received, then a single cycle pulse will be emitted from overrun_error and the word is discarded. If the receiver does not get a stop bit of the right level, then a single pulse will be emitted from the frame_error output and the received word will be discarded. | ||
| - | ===== Source Files ===== | + | ==== Source Files ==== |
| <code> | <code> | ||