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Verilog UART Readme

Introduction

This is a basic UART to AXI Stream IP core, written in Verilog with MyHDL testbenches.

Documentation

Source Files

rtl/uart.v - Wrapper for complete UART
rtl/uart_rx.v - UART receiver implementation
rtl/uart_tx.v - UART transmitter implementation

uart module

parameter DATA_WIDTH = 8 - define width of data bus and transferred words in bits
input wire clk - clock input
input wire rst - reset input
input wire [DATA_WIDTH-1:0] input_axis_tdata - data input
input wire input_axis_tvalid - data valid input
output wire input_axis_tready - ready for data output
output wire [DATA_WIDTH-1:0] output_axis_tdata - data output
output wire output_axis_tvalid - data valid output
input wire output_axis_tready - ready for data input
input wire rxd - UART RXD input
output wire txd - UART TXD output
output wire tx_busy - operation in progress signal
output wire rx_busy - operation in progress signal
output wire rx_overrun_error - overrun error signal
output wire rx_frame_error - frame error signal
input wire [15:0] prescale - BAUD rate prescale value

uart_rx module

parameter DATA_WIDTH = 8 - define width of data bus and transferred words in bits
input wire clk - clock input
input wire rst - reset input
output wire [DATA_WIDTH-1:0] output_axis_tdata - data output
output wire output_axis_tvalid - data valid output
input wire output_axis_tready - ready for data input
input wire rxd - UART RXD input
output wire busy - operation in progress signal
output wire overrun_error - overrun error signal
output wire frame_error - frame error signal
input wire [15:0] prescale - BAUD rate prescale value

uart_tx module

parameter DATA_WIDTH = 8 - define width of data bus and transferred words in bits
input wire clk - clock input
input wire rst - reset input
input wire [DATA_WIDTH-1:0] input_axis_tdata - data input
input wire input_axis_tvalid - data valid input
output wire input_axis_tready - ready for data output
output wire txd - UART TXD output
output wire busy - operation in progress signal
input wire [15:0] prescale - BAUD rate prescale value

AXI interface

The main interface to the user design is an AXI4-Stream interface that consists of the tdata, tvalid, and tready signals. tready flows in the opposite direction. tdata is considered valid when tvalid is high. The destination will accept data only when tready is high. Data is transferred from the source to the destination only when both tvalid and tready are high, otherwise the bus is stalled.

AXI Stream Interface Example

two byte transfer with sink pause after each byte

              __    __    __    __    __    __    __    __    __
    clk    __/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__
                    _____ _________________
    tdata  XXXXXXXXX_D0__X_D1______________XXXXXXXXXXXXXXXXXXXXXXXX
                    _______________________
    tvalid ________/                       \_______________________
           ______________             _____             ___________
    tready               \___________/     \___________/

Testing

Running the included testbenches requires MyHDL and Icarus Verilog. Make sure that myhdl.vpi is installed properly for cosimulation to work correctly. The testbenches can be run with a Python test runner like nose or py.test, or the individual test scripts can be run with python directly.

Testbench Files

tb/axis_ep.py - MyHDL AXI Stream endpoints
tb/test_uart_rx.py - MyHDL testbench for uart_rx module
tb/test_uart_rx.v - Verilog toplevel file for uart_rx cosimulation
tb/test_uart_tx.py - MyHDL testbench for uart_tx module
tb/test_uart_tx.v - Verilog toplevel file for uart_tx cosimulation
tb/uart_ep.py - MyHDL UART endpoints

Example Design

The included example design is targeted to a Digilent Atlys board. To build it, cd into example/ATLYS/fpga, make sure the Xilinx settings file has been sourced correctly, and run make.