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--- en:verilog:uart:readme [2014/11/09 08:47]
alex [Testbench Files]
+++ en:verilog:uart:readme [2014/11/09 09:39] (current)
alex [Source Files]
@@ Line 7: / Line 7: @@
 ===== Documentation =====
-==== Source Files ====
+The main code for the core exists in the rtl subdirectory.  The uart_rx.v and uart_tx.v files are the actual implementation, uart.v simply instantiates both modules and makes a couple of internal connections.
-  * ''rtl/uart.v'' - Wrapper for complete UART
+The UART transmitter and receiver both use a single transmit or receive pin.  The modules take one parameter, DATA_WIDTH, that specifies the width of both the data bus and the length of the actual data words communicated.  The default value is 8 for an 8 bit interface.  The prescale input determines the data rate - it should be set to Fclk / (baud * 8).  This is an input instead of a parameter so it can be changed at run time, though it is not buffered internally so care should be used to avoid corrupt data.  The main interface to the user design is an AXI4-Stream interface that consists of the tdata, tvalid, and tready signals.  tready flows in the opposite direction.  tdata is considered valid when tvalid is high.  The destination will accept data only when tready is high.  Data is transferred from the source to the destination only when both tvalid and tready are high, otherwise the bus is
-  * ''rtl/uart_rx.v'' - UART receiver implementation
+stalled.
-  * ''rtl/uart_tx.v'' - UART transmitter implementation
-==== uart module ====
+Both interfaces also present a 'busy' signal that is high when an operation is taking place.  The receiver also presents overrun error and frame error strobe outputs.  If the data word currently in the tdata output register is not read before another word is received, then a single cycle pulse will be emitted from overrun_error and the word is discarded.  If the receiver does not get a stop bit of the right level, then a single pulse will be emitted from the frame_error output and the received word will be discarded.
-  * ''parameter DATA_WIDTH = 8'' - define width of data bus and transferred words in bits
+==== Source Files ====
-  * ''input wire clk'' - clock input
-  * ''input wire rst'' - reset input
-  * ''input wire [DATA_WIDTH-1:0] input_axis_tdata'' - data input
-  * ''input wire input_axis_tvalid'' - data valid input
-  * ''output wire input_axis_tready'' - ready for data output
-  * ''output wire [DATA_WIDTH-1:0] output_axis_tdata'' - data output
-  * ''output wire output_axis_tvalid'' - data valid output
-  * ''input wire output_axis_tready'' - ready for data input
-  * ''input wire rxd'' - UART RXD input
-  * ''output wire txd'' - UART TXD output
-  * ''output wire tx_busy'' - operation in progress signal
-  * ''output wire rx_busy'' - operation in progress signal
-  * ''output wire rx_overrun_error'' - overrun error signal
-  * ''output wire rx_frame_error'' - frame error signal
-  * ''input wire [15:0] prescale'' - BAUD rate prescale value
-==== uart_rx module ====
+<code>
+    rtl/uart.v     : Wrapper for complete UART
-  * ''parameter DATA_WIDTH = 8'' - define width of data bus and transferred words in bits
+    rtl/uart_rx.v  : UART receiver implementation
-  * ''input wire clk'' - clock input
+    rtl/uart_tx.v  : UART transmitter implementation
-  * ''input wire rst'' - reset input
+</code>
-  * ''output wire [DATA_WIDTH-1:0] output_axis_tdata'' - data output
-  * ''output wire output_axis_tvalid'' - data valid output
-  * ''input wire output_axis_tready'' - ready for data input
-  * ''input wire rxd'' - UART RXD input
-  * ''output wire busy'' - operation in progress signal
-  * ''output wire overrun_error'' - overrun error signal
-  * ''output wire frame_error'' - frame error signal
-  * ''input wire [15:0] prescale'' - BAUD rate prescale value
-==== uart_tx module ====
+===== AXI interface =====
-  * ''parameter DATA_WIDTH = 8'' - define width of data bus and transferred words in bits
-  * ''input wire clk'' - clock input
-  * ''input wire rst'' - reset input
-  * ''input wire [DATA_WIDTH-1:0] input_axis_tdata'' - data input
-  * ''input wire input_axis_tvalid'' - data valid input
-  * ''output wire input_axis_tready'' - ready for data output
-  * ''output wire txd'' - UART TXD output
-  * ''output wire busy'' - operation in progress signal
-  * ''input wire [15:0] prescale'' - BAUD rate prescale value
-==== AXI interface ====
 The main interface to the user design is an AXI4-Stream interface that consists of the tdata, tvalid, and tready signals.  tready flows in the opposite direction.  tdata is considered valid when tvalid is high.  The destination will accept data only when tready is high.  Data is transferred from the source to the destination only when both tvalid and tready are high, otherwise the bus is stalled.
-=== AXI Stream Interface Example ===
+==== AXI Stream Interface Example ====
 two byte transfer with sink pause after each byte
@@ Line 83: / Line 47: @@
 ==== Testbench Files ====
-  * ''tb/axis_ep.py'' - MyHDL AXI Stream endpoints
+<code>
-  * ''tb/test_uart_rx.py'' - MyHDL testbench for uart_rx module
+    tb/axis_ep.py        : MyHDL AXI Stream endpoints
-  * ''tb/test_uart_rx.v'' - Verilog toplevel file for uart_rx cosimulation
+    tb/test_uart_rx.py   : MyHDL testbench for uart_rx module
-  * ''tb/test_uart_tx.py'' - MyHDL testbench for uart_tx module
+    tb/test_uart_rx.v    : Verilog toplevel file for uart_rx cosimulation
-  * ''tb/test_uart_tx.v'' - Verilog toplevel file for uart_tx cosimulation
+    tb/test_uart_tx.py   : MyHDL testbench for uart_tx module
-  * ''tb/uart_ep.py'' - MyHDL UART endpoints
+    tb/test_uart_tx.v    : Verilog toplevel file for uart_tx cosimulation
+    tb/uart_ep.py        : MyHDL UART endpoints
+</code>
 ===== Example Design =====