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en:verilog:uart:readme [2014/11/09 09:24] alex |
en:verilog:uart:readme [2014/11/09 09:27] alex [Signals and Parameters] |
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| ==== Source Files ==== | ==== Source Files ==== | ||
| - | * ''rtl/uart.v'' - Wrapper for complete UART | + | <code> |
| - | * ''rtl/uart_rx.v'' - UART receiver implementation | + | rtl/uart.v : Wrapper for complete UART |
| - | * ''rtl/uart_tx.v'' - UART transmitter implementation | + | rtl/uart_rx.v : UART receiver implementation |
| + | rtl/uart_tx.v : UART transmitter implementation | ||
| + | </code> | ||
| ===== uart module ===== | ===== uart module ===== | ||
| Line 17: | Line 19: | ||
| ==== Signals and Parameters ==== | ==== Signals and Parameters ==== | ||
| - | * Parameters | + | <code> |
| - | * ''parameter DATA_WIDTH = 8'' - define width of data bus and transferred words in bits | + | Parameters |
| - | * Clock and reset | + | parameter DATA_WIDTH = 8 - define width of data bus and transferred words in bits |
| - | * ''input wire clk'' - clock input | + | Clock and reset |
| - | * ''input wire rst'' - reset input | + | input wire clk - clock input |
| + | input wire rst - reset input | ||
| * AXI Stream Interface (TX) | * AXI Stream Interface (TX) | ||
| * ''input wire [DATA_WIDTH-1:0] input_axis_tdata'' - data input | * ''input wire [DATA_WIDTH-1:0] input_axis_tdata'' - data input | ||
| Line 40: | Line 43: | ||
| * Configuration | * Configuration | ||
| * ''input wire [15:0] prescale'' - BAUD rate prescale value | * ''input wire [15:0] prescale'' - BAUD rate prescale value | ||
| + | </code> | ||
| ==== Description ==== | ==== Description ==== | ||