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en:verilog:uart:readme [2014/11/09 09:24]
alex
en:verilog:uart:readme [2014/11/09 09:26]
alex [Source Files]
Line 12: Line 12:
   * ''​rtl/​uart_rx.v''​ - UART receiver implementation   * ''​rtl/​uart_rx.v''​ - UART receiver implementation
   * ''​rtl/​uart_tx.v''​ - UART transmitter implementation   * ''​rtl/​uart_tx.v''​ - UART transmitter implementation
 +
 +<​code>​
 +    rtl/​uart.v ​    : Wrapper for complete UART
 +    rtl/​uart_rx.v ​ : UART receiver implementation
 +    rtl/​uart_tx.v ​ : UART transmitter implementation
 +</​code>​
  
 ===== uart module ===== ===== uart module =====