Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision Both sides next revision
en:verilog:uart:readme [2014/11/09 09:08]
alex [uart_rx module]
en:verilog:uart:readme [2014/11/09 09:08]
alex [''uart_rx'' module]
Line 41: Line 41:
 The ''​uart''​ module is simply a wrapper around the ''​uart_rx''​ and ''​uart_tx''​ modules.  ​ The ''​uart''​ module is simply a wrapper around the ''​uart_rx''​ and ''​uart_tx''​ modules.  ​
  
-==== ''​uart_rx'' ​module ====+==== uart_rx module ====
  
 === Signals and Parameters === === Signals and Parameters ===