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en:verilog:uart:readme [2014/11/09 09:03] alex [uart_tx module] |
en:verilog:uart:readme [2014/11/09 09:07] alex [uart_rx module] |
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| ==== uart_rx module ==== | ==== uart_rx module ==== | ||
| + | |||
| + | === Signals and Parameters === | ||
| * Parameters | * Parameters | ||
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| * Configuration | * Configuration | ||
| * ''input wire [15:0] prescale'' - BAUD rate prescale value | * ''input wire [15:0] prescale'' - BAUD rate prescale value | ||
| + | |||
| + | === Description === | ||
| + | |||
| + | The ''uart_rx'' module implements the UART receive function. Bits received over the ''rxd'' pin are decoded and output on the AXI Stream interface. The baud rate is determined by the ''prescale'' setting, which should be set to Fclk / (baud * 8). ''prescale'' is a port and not a parameter so it can be changed at run time if necessary. The ''uart_rx'' module also generates frame and overrun error signals. The ''frame_error'' signal indicates that the stop bit was not received correctly, while the ''overrun_error'' signal indicates that a byte was received before the previous one was read, causing the older data byte to be overwritten. | ||
| ==== uart_tx module ==== | ==== uart_tx module ==== | ||