Differences

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--- en:verilog:uart:readme [2014/11/09 09:01]
alex [uart module]
+++ en:verilog:uart:readme [2014/11/09 09:08]
alex [''uart_rx'' module]
@@ Line 43: / Line 43: @@
 ==== uart_rx module ====
-  * ''parameter DATA_WIDTH = 8'' - define width of data bus and transferred words in bits
+=== Signals and Parameters ===
-  * ''input wire clk'' - clock input
-  * ''input wire rst'' - reset input
+  * Parameters
-  * ''output wire [DATA_WIDTH-1:0] output_axis_tdata'' - data output
+    * ''parameter DATA_WIDTH = 8'' - define width of data bus and transferred words in bits
-  * ''output wire output_axis_tvalid'' - data valid output
+  * Clock and Reset
-  * ''input wire output_axis_tready'' - ready for data input
+    * ''input wire clk'' - clock input
-  * ''input wire rxd'' - UART RXD input
+    * ''input wire rst'' - reset input
-  * ''output wire busy'' - operation in progress signal
+  * AXI Stream Interface
-  * ''output wire overrun_error'' - overrun error signal
+    * ''output wire [DATA_WIDTH-1:0] output_axis_tdata'' - data output
-  * ''output wire frame_error'' - frame error signal
+    * ''output wire output_axis_tvalid'' - data valid output
-  * ''input wire [15:0] prescale'' - BAUD rate prescale value
+    * ''input wire output_axis_tready'' - ready for data input
+  * UART Interface
+    * ''input wire rxd'' - UART RXD input
+  * Status
+    * ''output wire busy'' - operation in progress signal
+    * ''output wire overrun_error'' - overrun error signal
+    * ''output wire frame_error'' - frame error signal
+  * Configuration
+    * ''input wire [15:0] prescale'' - BAUD rate prescale value
+=== Description ===
+The ''uart_rx'' module implements the UART receive function.  Bits received over the ''rxd'' pin are decoded and output on the AXI Stream interface.  The baud rate is determined by the ''prescale'' setting, which should be set to Fclk / (baud * 8).  ''prescale'' is a port and not a parameter so it can be changed at run time if necessary.  The ''uart_rx'' module also generates frame and overrun error signals.  The ''frame_error'' signal indicates that the stop bit was not received correctly, while the ''overrun_error'' signal indicates that a byte was received before the previous one was read, causing the older data byte to be overwritten.
 ==== uart_tx module ====
-  * ''parameter DATA_WIDTH = 8'' - define width of data bus and transferred words in bits
+  * Parameters
-  * ''input wire clk'' - clock input
+    * ''parameter DATA_WIDTH = 8'' - define width of data bus and transferred words in bits
-  * ''input wire rst'' - reset input
+  * Clock and Reset
-  * ''input wire [DATA_WIDTH-1:0] input_axis_tdata'' - data input
+    * ''input wire clk'' - clock input
-  * ''input wire input_axis_tvalid'' - data valid input
+    * ''input wire rst'' - reset input
-  * ''output wire input_axis_tready'' - ready for data output
+  * AXI Stream Interface
-  * ''output wire txd'' - UART TXD output
+    * ''input wire [DATA_WIDTH-1:0] input_axis_tdata'' - data input
-  * ''output wire busy'' - operation in progress signal
+    * ''input wire input_axis_tvalid'' - data valid input
-  * ''input wire [15:0] prescale'' - BAUD rate prescale value
+    * ''output wire input_axis_tready'' - ready for data output
+  * UART Interface
+    * ''output wire txd'' - UART TXD output
+  * Status
+    * ''output wire busy'' - operation in progress signal
+  * Configuration
+    * ''input wire [15:0] prescale'' - BAUD rate prescale value
 ==== AXI interface ====