Writing /var/www/alexforencich.com/wiki/data/cache/e/ef89ba0c5e9bf1d73aff26911e5db02d.metadata failed
Writing /var/www/alexforencich.com/wiki/data/cache/5/547b5b92dcc0a428238b5bdf13eb8625.xhtml failed

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
en:verilog:start [2019/05/28 10:20]
alex
en:verilog:start [2019/07/12 21:28] (current)
alex
Line 6: Line 6:
   * [[.:i2c:]]   * [[.:i2c:]]
   * [[.:​mersenne:​]]   * [[.:​mersenne:​]]
 +  * [[.:pcie:]]
   * [[.:uart:]]   * [[.:uart:]]
   * [[.:​wishbone:​]]   * [[.:​wishbone:​]]