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en:verilog:start [2019/05/28 10:20]
alex
en:verilog:start [2019/07/12 21:28] (current)
alex
Line 6: Line 6:
   * [[.:i2c:]]   * [[.:i2c:]]
   * [[.:​mersenne:​]]   * [[.:​mersenne:​]]
 +  * [[.:pcie:]]
   * [[.:uart:]]   * [[.:uart:]]
   * [[.:​wishbone:​]]   * [[.:​wishbone:​]]