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en:verilog:start [2019/04/04 04:47] alexen:verilog:start [2019/07/12 19:28] (current) alex
Line 4: Line 4:
   * [[.:axis:]]   * [[.:axis:]]
   * [[.:ethernet:]]   * [[.:ethernet:]]
 +  * [[.:i2c:]]
   * [[.:mersenne:]]   * [[.:mersenne:]]
 +  * [[.:pcie:]]
   * [[.:uart:]]   * [[.:uart:]]
   * [[.:wishbone:]]   * [[.:wishbone:]]