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en:verilog:start [2014/11/09 07:57] alex |
en:verilog:start [2019/04/04 06:46] alex |
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| ====== Verilog IP cores ====== | ====== Verilog IP cores ====== | ||
| + | * [[.:axi:]] | ||
| * [[.:axis:]] | * [[.:axis:]] | ||
| * [[.:ethernet:]] | * [[.:ethernet:]] | ||