Verilog Mersenne Twister PRNG

Mersenne Twister PRNG with an AXI4-Stream interface. Includes both 32 bit (mt19937ar) and 64 bit (mt19937-64) implementations along with original C and Python references. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.

32 bit version on a Spartan 6: 175 MHz, 4 BRAMs, 226 FFs, 412 LUTs

64 bit version on a Spartan 6: 175 MHz, 4 BRAMs, 388 FFs, 829 LUTs

• Verilog Mersenne Twister on GitHub

• Icarus Verilog simulator
• MyHDL
• Mersenne Twister PRNG