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en:verilog:mersenne:start [2014/09/17 03:24] alex [Introduction] |
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| ===== Introduction ===== | ===== Introduction ===== | ||
| - | Mersenne Twister PRNG with an AXI4-Stream interface. Data can be read out on every cycle after seeding completes, resulting in 11.2 Gbps when running at 175 MHz. Includes both 32 bit (mt19937ar) and 64 bit (mt19937-64) implementations along with original C and Python implementations. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. | + | Mersenne Twister PRNG with an AXI4-Stream interface. Data can be read out on every cycle after seeding completes, resulting in 5.6 Gbps for the 32 bit version and 11.2 Gbps for the 64 bit version when running at 175 MHz. Includes both 32 bit (mt19937ar) and 64 bit (mt19937-64) synthesizable verilog implementations along with reference C and Python implementations. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. |
| 32 bit version on a Spartan 6: 175 MHz, 4 BRAMs, 226 FFs, 412 LUTs | 32 bit version on a Spartan 6: 175 MHz, 4 BRAMs, 226 FFs, 412 LUTs | ||
| 64 bit version on a Spartan 6: 175 MHz, 4 BRAMs, 388 FFs, 829 LUTs | 64 bit version on a Spartan 6: 175 MHz, 4 BRAMs, 388 FFs, 829 LUTs | ||
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| + | ===== Documentation ===== | ||
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| + | [[readme]] | ||
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| ===== Repository ===== | ===== Repository ===== | ||