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en:verilog:i2c:start [2019/05/28 10:21] (current)
alex created
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 +====== Verilog UART ======
 +
 +===== Introduction =====
 +
 +I2C interface components. ​ Includes full MyHDL testbench with intelligent bus cosimulation endpoints.
 +
 +===== Documentation =====
 +
 +[[readme]]
 +
 +===== Repository =====
 +
 +  * [[http://​github.com/​alexforencich/​verilog-i2c/​|Verilog I2C on GitHub]]
 +
 +===== Links =====
 +
 +  * [[http://​iverilog.icarus.com/​|Icarus Verilog simulator]]
 +  * [[http://​www.myhdl.org/​|MyHDL]]
  
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