Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
en:verilog:ethernet:start [2019/04/04 07:23]
alex [Verilog Ethernet Stack]
en:verilog:ethernet:start [2019/07/12 21:29]
alex
Line 3: Line 3:
 ===== Introduction ===== ===== Introduction =====
  
-Ethernet ​stack with UDP/​IP ​components ​in 8 bit and 64 bit AXI4-stream ​datapaths ​for 1G or 10G line rate processing Includes ​LocalLink ​and Avalon bridges ​for use with all standard Xilinx ​and Altera tri-mode ​and 10G MACs ​Includes ​full MyHDL testbench with intelligent bus cosimulation endpoints. ​ +Collection of Ethernet-related ​components ​for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). Includes ​modules for handling Ethernet frames as well as IP, UDP, and ARP and the components ​for constructing a complete UDP/IP stack. Includes MAC modules for gigabit ​and 10G, a 10G PCS/PMA PHY module, ​and 10G combination MAC/PCS/PMA moduleAlso includes ​full MyHDL testbench with intelligent bus cosimulation endpoints.
  
 ===== Documentation ===== ===== Documentation =====
Recent changes RSS feed Creative Commons License Donate Minima Template by Wikidesign Driven by DokuWiki