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en:verilog:ethernet:start [2014/09/09 04:50] alex [Introduction] |
en:verilog:ethernet:start [2014/11/20 02:15] alex [Introduction] |
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| Ethernet stack with UDP/IP components in 8 bit and 64 bit AXI4-stream datapaths for 1G or 10G line rate processing. Includes LocalLink and Avalon bridges for use with all standard Xilinx and Altera tri-mode and 10G MACs. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. | Ethernet stack with UDP/IP components in 8 bit and 64 bit AXI4-stream datapaths for 1G or 10G line rate processing. Includes LocalLink and Avalon bridges for use with all standard Xilinx and Altera tri-mode and 10G MACs. Includes full MyHDL testbench with intelligent bus cosimulation endpoints. | ||
| + | ===== Documentation ===== | ||
| + | |||
| + | [[readme]] | ||
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| + | ===== Repository ===== | ||
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| + | * [[https://github.com/alexforencich/verilog-ethernet]] | ||
| ===== Links ===== | ===== Links ===== | ||