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en:verilog:ethernet:readme [2014/11/20 02:25]
alex created 		en:verilog:ethernet:readme [2019/04/04 07:34]
alex
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 ====== Verilog Ethernet Components Readme ====== ====== Verilog Ethernet Components Readme ======
 +
 +For more information and updates: http://​alexforencich.com/​wiki/​en/​verilog/​ethernet/​start
 +
 +GitHub repository: https://​github.com/​alexforencich/​verilog-ethernet
  
 ===== Introduction ===== ===== Introduction =====
  
-Collection of Ethernet-related components for both gigabit and 10G packet processing (8 bit and 64 bit datapaths). ​ Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. ​ Includes full MyHDL testbench with intelligent bus cosimulation endpoints.+Collection of Ethernet-related components for both gigabit and 10G packet 
 +processing (8 bit and 64 bit datapaths). ​ Includes modules for handling 
 +Ethernet frames as well as IP, UDP, and ARP and the components for 
 +constructing a complete UDP/IP stack. ​ Includes ​MAC modules for gigabit and 
 +10G, a 10G PCS/PMA PHY module, and a 10G combination MAC/PCS/PMA module. ​ Also 
 +includes ​full MyHDL testbench with intelligent bus cosimulation endpoints. 
 + 
 +For IP and ARP support only, use ip_complete (1G) or ip_complete_64 (10G). 
 + 
 +For UDP, IP, and ARP support, use udp_complete (1G) or udp_complete_64 (10G). 
 + 
 +Top level gigabit and 10G MAC modules are eth_mac_*, with various interfaces 
 +and with/​without FIFOs. ​ Top level 10G PCS/PMA PHY module is eth_phy_10g. ​ Top 
 +level 10G MAC/PCS/PMA combination module is eth_mac_phy_10g.
  
 ===== Documentation ===== ===== Documentation =====
 +
 +==== arp module ====
 +
 +ARP handling logic with parametrizable retry timeout parameters.
 +
 +==== arp_64 module ====
 +
 +ARP handling logic with parametrizable retry timeout parameters and 64 bit
 +datapath for 10G Ethernet.
 +
 +==== arp_cache module ====
 +
 +Basic hash-based cache for ARP entries. ​ Parametrizable depth.  ​
  
 ==== arp_eth_rx module ==== ==== arp_eth_rx module ====
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 ARP frame transmitter with 64 bit datapath for 10G Ethernet. ARP frame transmitter with 64 bit datapath for 10G Ethernet.
  
-==== eth_arb_mux_N ​module ====+==== axis_eth_fcs module ==== 
 + 
 +Ethernet frame check sequence calculator. 
 + 
 +==== axis_eth_fcs_64 module ==== 
 + 
 +Ethernet frame check sequence calculator with 64 bit datapath for 10G Ethernet. 
 + 
 +==== axis_eth_fcs_check module ==== 
 + 
 +Ethernet frame check sequence checker. 
 + 
 +==== axis_eth_fcs_insert module ==== 
 + 
 +Ethernet frame check sequence inserter. 
 + 
 +==== axis_gmii_rx module ==== 
 + 
 +AXI stream GMII/MII frame receiver with clock enable and MII select. 
 + 
 +==== axis_gmii_tx module ==== 
 + 
 +AXI stream GMII/MII frame transmitter with clock enable and MII select. 
 + 
 +==== axis_xgmii_rx_32 module ==== 
 + 
 +AXI stream XGMII frame receiver with 32 bit datapath. 
 + 
 +==== axis_xgmii_rx_64 module ==== 
 + 
 +AXI stream XGMII frame receiver with 64 bit datapath. 
 + 
 +==== axis_xgmii_tx_32 ​module ====
  
-Ethernet ​frame arbitrated muliplexer ​with 8 bit data width for gigabit Ethernet. ​ Supports priority and round-robin arbitration.+AXI stream XGMII frame transmitter ​with 32 bit datapath.
  
-Can be generated with arbitrary port counts with eth_arb_mux.py.+==== axis_xgmii_tx_64 module ====
  
-==== eth_arb_mux_64_N module ====+AXI stream XGMII frame transmitter with 64 bit datapath.
  
-Ethernet frame arbitrated muliplexer with 8 bit data width for 10G Ethernet. ​ Supports priority and round-robin arbitration.+==== eth_arb_mux module ====
  
-Can be generated ​with arbitrary ​port counts with eth_arb_mux_64.py.+Ethernet frame arbitrated muliplexer ​with parametrizable data width and port 
 +count.  ​Supports priority and round-robin arbitration.
  
 ==== eth_axis_rx module ==== ==== eth_axis_rx module ====
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 Ethernet frame transmitter with 64 bit datapath for 10G Ethernet. Ethernet frame transmitter with 64 bit datapath for 10G Ethernet.
  
-==== eth_demux_N ​module ====+==== eth_demux ​module ====
  
-Ethernet frame demuliplexer with 8 bit data width for gigabit Ethernet.  Supports priority and round-robin arbitration.+Ethernet frame demuliplexer with parametrizable ​data width and port count. 
 +Supports priority and round-robin arbitration.
  
-Can be generated with arbitrary port counts with eth_demux.py.+==== eth_mac_1g module ====
  
-==== eth_demux_64_N module ====+Gigabit Ethernet MAC with GMII interface.
  
-Ethernet frame demuliplexer with 64 bit data width for 10G Ethernet. ​ Supports priority and round-robin arbitration.+==== eth_mac_1g_fifo module ====
  
-Can be generated ​with arbitrary port counts with eth_demux_64.py.+Gigabit Ethernet MAC with GMII interface and FIFOs.
  
-==== eth_mux_N ​module ====+==== eth_mac_1g_gmii ​module ====
  
-Ethernet ​frame muliplexer ​with 8 bit data width for gigabit Ethernet. ​ Supports priority ​and round-robin arbitration.+Tri-mode ​Ethernet ​MAC with GMII/MII interface ​and automatic PHY rate 
 +adaptation logic.
  
-Can be generated with arbitrary port counts with eth_mux.py.+==== eth_mac_1g_gmii_fifo module ====
  
-==== eth_mux_64_N module ====+Tri-mode Ethernet MAC with GMII/MII interface, FIFOs, and automatic PHY rate 
 +adaptation logic.
  
-Ethernet frame muliplexer with 64 bit data width for 10G Ethernet. ​ Supports priority and round-robin arbitration.+==== eth_mac_1g_rgmii module ====
  
-Can be generated ​with arbitrary port counts ​with eth_mux_64.py.+Tri-mode Ethernet MAC with RGMII interface and automatic PHY rate adaptation 
 +logic. 
 + 
 +==== eth_mac_1g_rgmii_fifo module ==== 
 + 
 +Tri-mode Ethernet MAC with RGMII interface, FIFOs, and automatic PHY rate 
 +adaptation logic. 
 + 
 +==== eth_mac_10g module ==== 
 + 
 +10G Ethernet MAC with XGMII interface. ​ Datapath selectable between 32 and 64 
 +bits. 
 + 
 +==== eth_mac_10g_fifo module ==== 
 + 
 +10G Ethernet MAC with XGMII interface and FIFOs. ​ Datapath selectable between 
 +32 and 64 bits. 
 + 
 +==== eth_mac_mii module ==== 
 + 
 +Ethernet MAC with MII interface. 
 + 
 +==== eth_mac_mii_fifo module ==== 
 + 
 +Ethernet MAC with MII interface and FIFOs. 
 + 
 +==== eth_mac_phy_10g module ==== 
 + 
 +10G Ethernet MAC/PHY combination module with SERDES interface. 
 + 
 +==== eth_mac_phy_10g_fifo module ==== 
 + 
 +10G Ethernet MAC/PHY combination module with SERDES interface and FIFOs. 
 + 
 +==== eth_mac_phy_10g_rx module ==== 
 + 
 +10G Ethernet MAC/PHY combination module with SERDES interface, RX path. 
 + 
 +==== eth_mac_phy_10g_tx module ==== 
 + 
 +10G Ethernet MAC/PHY combination module with SERDES interface, TX path. 
 + 
 +==== eth_mux module ==== 
 + 
 +Ethernet frame muliplexer with parametrizable data width and port count. 
 +Supports priority and round-robin arbitration. 
 + 
 +==== eth_phy_10g module ==== 
 + 
 +10G Ethernet PCS/PMA PHY. 
 + 
 +==== eth_phy_10g_rx module ==== 
 + 
 +10G Ethernet PCS/PMA PHY receive-side logic. 
 + 
 +==== eth_phy_10g_rx_ber_mon module ==== 
 + 
 +10G Ethernet PCS/PMA PHY BER monitor. 
 + 
 +==== eth_phy_10g_rx_frame_sync module ==== 
 + 
 +10G Ethernet PCS/PMA PHY frame synchronizer. 
 + 
 +==== eth_phy_10g_tx module ==== 
 + 
 +10G Ethernet PCS/PMA PHY transmit-side logic. 
 + 
 +==== gmii_phy_if module ==== 
 + 
 +GMII/MII PHY interface and clocking logic.
  
 ==== ip module ==== ==== ip module ====
  
-IPv4 block with 8 bit data width for gigabit Ethernet. ​ Manages IPv4 packet transmssion and reception. ​ Interfaces with ARP module for MAC address lookup.+IPv4 block with 8 bit data width for gigabit Ethernet. ​ Manages IPv4 packet 
 +transmssion and reception. ​ Interfaces with ARP module for MAC address lookup.
  
 ==== ip_64 module ==== ==== ip_64 module ====
  
-IPv4 block with 64 bit data width for 10G Ethernet. ​ Manages IPv4 packet transmssion and reception. ​ Interfaces with ARP module for MAC address lookup.+IPv4 block with 64 bit data width for 10G Ethernet. ​ Manages IPv4 packet 
 +transmssion and reception. ​ Interfaces with ARP module for MAC address lookup.
  
-==== ip_arb_mux_N ​module ====+==== ip_arb_mux ​module ====
  
-IP frame arbitrated muliplexer with 8 bit data width for gigabit +IP frame arbitrated muliplexer with parametrizable ​data width and port count. 
-Ethernet.  Supports priority and round-robin arbitration.+Supports priority and round-robin arbitration.
  
-Can be generated with arbitrary port counts with ip_arb_mux.py.+==== ip_complete module ====
  
-==== ip_arb_mux_64_N ​module ​====+IPv4 module ​with ARP integration.
  
-IP frame arbitrated muliplexer with 8 bit data width for 10G Ethernet. ​ Supports priority and round-robin arbitration.+Top level for gigabit IP stack.
  
-Can be generated ​with arbitrary port counts ​with ip_arb_mux_64.py.+==== ip_complete_64 module ==== 
 + 
 +IPv4 module ​with ARP integration and 64 bit data width for 10G Ethernet. 
 + 
 +Top level for 10G IP stack. 
 + 
 +==== ip_demux module ==== 
 + 
 +IP frame demuliplexer ​with parametrizable data width and port count. 
 +Supports priority and round-robin arbitration.
  
 ==== ip_eth_rx module ==== ==== ip_eth_rx module ====
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 IP frame transmitter with 64 bit datapath for 10G Ethernet. IP frame transmitter with 64 bit datapath for 10G Ethernet.
  
-==== ip_demux_N ​module ====+==== ip_mux ​module ====
  
-IP frame demuliplexer ​with 8 bit data width for gigabit Ethernet.  Supports priority and round-robin arbitration.+IP frame muliplexer ​with parametrizable ​data width and port count. 
 +Supports priority and round-robin arbitration.
  
-Can be generated with arbitrary port counts with ip_demux.py.+==== lfsr module ====
  
-==== ip_demux_64_N ​module ​====+Fully parametrizable combinatorial parallel LFSR/​CRC ​module.
  
-IP frame demuliplexer with 64 bit data width for 10G Ethernet. ​ Supports priority and round-robin arbitration.+==== mii_phy_if module ====
  
-Can be generated with arbitrary port counts with ip_demux_64.py.+MII PHY interface and clocking logic.
  
-==== ip_mux_N ​module ====+==== rgmii_phy_if ​module ====
  
-IP frame muliplexer with 8 bit data width for gigabit Ethernet. ​ Supports priority ​and round-robin arbitration.+RGMII PHY interface ​and clocking logic.
  
-Can be generated with arbitrary port counts with ip_mux.py.+==== udp module ====
  
-==== ip_mux_64_N module ====+UDP block with 8 bit data width for gigabit Ethernet. ​ Manages UDP packet 
 +transmssion and reception.
  
-IP frame muliplexer with 64 bit data width for 10G Ethernet. ​ Supports priority and round-robin arbitration.+==== udp_64 module ====
  
-Can be generated ​with arbitrary port counts with ip_mux_64.py.+UDP block with 64 bit data width for 10G Ethernet.  ​Manages UDP packet 
 +transmssion and reception.
  
-==== udp_arb_mux_N ​module ====+==== udp_arb_mux ​module ====
  
-UDP frame arbitrated muliplexer with 8 bit data width for gigabit Ethernet.  Supports priority and round-robin arbitration.+UDP frame arbitrated muliplexer with parametrizable ​data width and port 
 +count.  Supports priority and round-robin arbitration.
  
-Can be generated with arbitrary port counts with udp_arb_mux.py.+==== udp_checksum_gen module ====
  
-==== udp_arb_mux_64_N ​module ​====+UDP checksum generator ​module.  Calculates UDP length, IP length, and 
 +UDP checksum fields.
  
-UDP frame arbitrated muliplexer with 8 bit data width for 10G Ethernet. ​ Supports priority and round-robin arbitration.+==== udp_checksum_gen_64 module ====
  
-Can be generated ​with arbitrary port counts ​with udp_arb_mux_64.py.+UDP checksum generator module ​with 64 bit datapath. ​ Calculates UDP 
 +length, IP length, and UDP checksum fields. 
 + 
 +==== udp_complete module ==== 
 + 
 +UDP module ​with IPv4 and ARP integration. 
 + 
 +Top level for gigabit UDP stack. 
 + 
 +==== udp_complete_64 module ==== 
 + 
 +UDP module with IPv4 and ARP integration and 64 bit data width for 10G 
 +Ethernet. 
 + 
 +Top level for 10G UDP stack. 
 + 
 +==== udp_demux module ==== 
 + 
 +UDP frame demuliplexer with parametrizable data width and port count. 
 +Supports priority and round-robin arbitration.
  
 ==== udp_ip_rx module ==== ==== udp_ip_rx module ====
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 UDP frame transmitter with 64 bit datapath for 10G Ethernet. UDP frame transmitter with 64 bit datapath for 10G Ethernet.
  
-==== udp_demux_N ​module ====+==== udp_mux ​module ====
  
-UDP frame demuliplexer ​with 8 bit data width for gigabit Ethernet. Supports priority and round-robin arbitration.+UDP frame muliplexer ​with parametrizable ​data width and port count. 
 +Supports priority and round-robin arbitration.
  
-Can be generated with arbitrary port counts with udp_demux.py.+==== xgmii_baser_dec_64 module ====
  
-==== udp_demux_64_N module ====+XGMII 10GBASE-R decoder for 10G PCS/PMA PHY.
  
-UDP frame demuliplexer with 64 bit data width for 10G Ethernet. ​ Supports priority and round-robin arbitration.+==== xgmii_baser_enc_64 module ====
  
-Can be generated with arbitrary port counts with udp_demux_64.py.+XGMII 10GBASE-R encoder for 10G PCS/PMA PHY.
  
-==== udp_mux_N ​module ====+==== xgmii_deinterleave ​module ====
  
-UDP frame muliplexer with 8 bit data width for gigabit Ethernet. Supports priority ​and round-robin arbitration.+XGMII de-interleaver ​for interfacing with PHY cores that interleave the 
 +control ​and data lines.
  
-Can be generated with arbitrary port counts with udp_mux.py.+==== xgmii_interleave module ====
  
-==== udp_mux_64_N module ==== +XGMII interleaver for interfacing with PHY cores that interleave the control 
- +and data lines.
-UDP frame muliplexer with 64 bit data width for 10G Ethernet. ​ Supports priority and round-robin arbitration. +
- +
-Can be generated with arbitrary port counts with udp_mux_64.py.+
  
 ==== Common signals ==== ==== Common signals ====
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 <​code>​ <​code>​
 +    rtl/​arp.v ​                      : ARP handling logic
 +    rtl/​arp_64.v ​                   : ARP handling logic (64 bit)
 +    rtl/​arp_cache.v ​                : ARP LRU cache
     rtl/​arp_eth_rx.v ​               : ARP frame receiver     rtl/​arp_eth_rx.v ​               : ARP frame receiver
     rtl/​arp_eth_rx_64.v ​            : ARP frame receiver (64 bit)     rtl/​arp_eth_rx_64.v ​            : ARP frame receiver (64 bit)
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     rtl/​arp_eth_tx_64.v ​            : ARP frame transmitter (64 bit)     rtl/​arp_eth_tx_64.v ​            : ARP frame transmitter (64 bit)
     rtl/​eth_arb_mux.py ​             : Ethernet frame arbitrated multiplexer generator     rtl/​eth_arb_mux.py ​             : Ethernet frame arbitrated multiplexer generator
-    rtl/eth_arb_mux_4.v             ​: 4 port Ethernet ​frame arbitrated multiplexer +    rtl/axis_eth_fcs.v              : Ethernet ​FCS calculator 
-    rtl/eth_arb_mux_64.py           : Ethernet ​frame arbitrated multiplexer generator ​(64 bit) +    rtl/axis_eth_fcs_64.v           : Ethernet ​FCS calculator ​(64 bit) 
-    rtl/eth_arb_mux_64_4.v          : 4 port Ethernet ​frame arbitrated multiplexer ​(64 bit)+    rtl/axis_eth_fcs_insert.v       ​: Ethernet ​FCS inserter 
 +    rtl/​axis_eth_fcs_check.v ​       : Ethernet FCS checker 
 +    rtl/​axis_gmii_rx.v ​             : AXI stream GMII/MII receiver 
 +    rtl/​axis_gmii_tx.v ​             : AXI stream GMII/MII transmitter 
 +    rtl/​axis_xgmii_rx_32.v ​         : AXI stream XGMII receiver (32 bit) 
 +    rtl/​axis_xgmii_rx_64.v ​         : AXI stream XGMII receiver ​(64 bit) 
 +    rtl/​axis_xgmii_tx_32.v ​         : AXI stream XGMII transmitter (32 bit) 
 +    rtl/​axis_xgmii_tx_64.v ​         : AXI stream XGMII transmitter (64 bit) 
 +    rtl/​eth_arb_mux.v ​              : Ethernet frame arbitrated multiplexer
     rtl/​eth_axis_rx.v ​              : Ethernet frame receiver     rtl/​eth_axis_rx.v ​              : Ethernet frame receiver
     rtl/​eth_axis_rx_64.v ​           : Ethernet frame receiver (64 bit)     rtl/​eth_axis_rx_64.v ​           : Ethernet frame receiver (64 bit)
     rtl/​eth_axis_tx.v ​              : Ethernet frame transmitter     rtl/​eth_axis_tx.v ​              : Ethernet frame transmitter
     rtl/​eth_axis_tx_64.v ​           : Ethernet frame transmitter (64 bit)     rtl/​eth_axis_tx_64.v ​           : Ethernet frame transmitter (64 bit)
-    rtl/​eth_demux.py                ​: Ethernet frame demultiplexer ​generator +    rtl/​eth_demux.v                 : Ethernet frame demultiplexer 
-    rtl/eth_demux_4.v               ​: 4 port Ethernet ​frame demultiplexer +    rtl/eth_mac_1g.v                : Gigabit ​Ethernet ​GMII MAC 
-    rtl/eth_demux_64.py             : Ethernet ​frame demultiplexer generator (64 bit) +    rtl/eth_mac_1g_fifo.v           : Gigabit ​Ethernet ​GMII MAC with FIFO 
-    rtl/eth_demux_64_4.v            : 4 port Ethernet ​frame demultiplexer (64 bit) +    rtl/eth_mac_1g_gmii.v           ​: Tri-mode ​Ethernet ​GMII/MII MAC 
-    rtl/eth_mux.py                  ​: Ethernet ​frame multiplexer generator +    rtl/eth_mac_1g_gmii_fifo.v      ​: Tri-mode ​Ethernet ​GMII/MII MAC with FIFO 
-    rtl/eth_mux_4.v                 ​: 4 port Ethernet ​frame multiplexer +    rtl/eth_mac_1g_rgmii.v          : Tri-mode ​Ethernet ​RGMII MAC 
-    rtl/eth_mux_64.py               : Ethernet ​frame multiplexer generator (64 bit) +    rtl/eth_mac_1g_rgmii_fifo.v     : Tri-mode Ethernet RGMII MAC with FIFO 
-    rtl/eth_mux_64_4.v              : 4 port Ethernet frame multiplexer ​(64 bit)+    rtl/​eth_mac_10g.v ​              : 10G Ethernet ​XGMII MAC 
 +    rtl/eth_mac_10g_fifo.v          : 10G Ethernet XGMII MAC with FIFO 
 +    rtl/​eth_mac_mii.v ​              : Ethernet MII MAC 
 +    rtl/​eth_mac_mii_fifo.v ​         : Ethernet MII MAC with FIFO 
 +    rtl/​eth_mac_phy_10g.v ​          : 10G Ethernet XGMII MAC/PHY 
 +    rtl/​eth_mac_phy_10g_fifo.v ​     : 10G Ethernet XGMII MAC/PHY with FIFO 
 +    rtl/​eth_mac_phy_10g_rx.v ​       : 10G Ethernet XGMII MAC/PHY RX with FIFO 
 +    rtl/​eth_mac_phy_10g_tx.v ​       : 10G Ethernet XGMII MAC/PHY TX with FIFO 
 +    rtl/​eth_mux.v ​                  : Ethernet frame multiplexer 
 +    rtl/​gmii_phy_if.v ​              : GMII PHY interface 
 +    rtl/​iddr.v ​                     : Generic DDR input register
     rtl/​ip.v ​                       : IPv4 block     rtl/​ip.v ​                       : IPv4 block
     rtl/​ip_64.v ​                    : IPv4 block (64 bit)     rtl/​ip_64.v ​                    : IPv4 block (64 bit)
-    rtl/​ip_arb_mux.py               : IP frame arbitrated multiplexer ​generator +    rtl/​ip_arb_mux.v                ​: IP frame arbitrated multiplexer 
-    rtl/ip_arb_mux_4.v              : 4 port IP frame arbitrated multiplexer +    rtl/ip_complete.v               ​: IPv4 stack (IP-ARP integration) 
-    rtl/ip_arb_mux_64.py            : IP frame arbitrated multiplexer generator ​(64 bit) +    rtl/ip_complete_64.v            : ​IPv4 stack (IP-ARP integration) ​(64 bit) 
-    rtl/ip_arb_mux_64_4.v           ​: 4 port IP frame arbitrated multiplexer (64 bit)+    rtl/ip_demux.v                  : IP frame demultiplexer
     rtl/​ip_eth_rx.v ​                : IPv4 frame receiver     rtl/​ip_eth_rx.v ​                : IPv4 frame receiver
     rtl/​ip_eth_rx_64.v ​             : IPv4 frame receiver (64 bit)     rtl/​ip_eth_rx_64.v ​             : IPv4 frame receiver (64 bit)
     rtl/​ip_eth_tx.v ​                : IPv4 frame transmitter     rtl/​ip_eth_tx.v ​                : IPv4 frame transmitter
     rtl/​ip_eth_tx_64.v ​             : IPv4 frame transmitter (64 bit)     rtl/​ip_eth_tx_64.v ​             : IPv4 frame transmitter (64 bit)
-    rtl/ip_demux.py                 : IP frame demultiplexer generator +    rtl/ip_mux.v                    ​: IP frame multiplexer 
-    rtl/ip_demux_4.v                : 4 port IP frame demultiplexer +    rtl/lfsr.v ​                     : Generic LFSR/CRC module 
-    rtl/ip_demux_64.py              : ​IP frame demultiplexer generator (64 bit) +    rtl/​oddr.v ​                     : Generic DDR output register 
-    rtl/ip_demux_64_4.v             ​: 4 port IP frame demultiplexer (64 bit) +    rtl/​mii_phy_if.v                : MII PHY interface 
-    rtl/ip_mux.py                   : IP frame multiplexer generator +    rtl/rgmii_phy_if.v              : ​RGMII PHY interface 
-    rtl/ip_mux_4.v                  : 4 port IP frame multiplexer +    rtl/ssio_ddr_in.v               ​: Generic source synchronous IO DDR input module 
-    rtl/ip_mux_64.py                ​: IP frame multiplexer generator (64 bit) +    rtl/ssio_ddr_in_diff.v          ​: Generic source synchronous IO DDR differential input module 
-    rtl/ip_mux_64_4.v               : ​4 port IP frame multiplexer ​(64 bit) +    rtl/ssio_ddr_out.v              : Generic source synchronous IO DDR output module 
-    rtl/​udp_arb_mux.py              ​: UDP frame arbitrated multiplexer ​generator +    rtl/ssio_ddr_out_diff.v         : Generic source synchronous IO DDR differential output module 
-    rtl/udp_arb_mux_4.v             ​: 4 port UDP frame arbitrated multiplexer +    rtl/ssio_sdr_in.v               : ​Generic source synchronous IO SDR input module 
-    rtl/udp_arb_mux_64.py           : UDP frame arbitrated multiplexer ​generator (64 bit) +    rtl/​ssio_sdr_in_diff.v ​         : Generic source synchronous IO SDR differential input module 
-    rtl/udp_arb_mux_64_4.v          : 4 port UDP frame arbitrated multiplexer ​(64 bit)+    rtl/​ssio_sdr_out.v ​             : Generic source synchronous IO SDR output module 
 +    rtl/​ssio_sdr_out_diff.v ​        : Generic source synchronous IO SDR differential output module 
 +    rtl/​udp.v ​                      : UDP block 
 +    rtl/​udp_64.v ​                   : UDP block (64 bit) 
 +    rtl/​udp_arb_mux.v               : UDP frame arbitrated multiplexer 
 +    rtl/udp_checksum_gen.v          : UDP checksum generator 
 +    rtl/udp_checksum_gen_64.v       : UDP checksum ​generator (64 bit) 
 +    rtl/udp_complete.v              : UDP stack (IP-ARP-UDP) 
 +    rtl/​udp_complete_64.v ​          : UDP stack (IP-ARP-UDP) ​(64 bit) 
 +    rtl/​udp_demux.v ​                : UDP frame demultiplexer
     rtl/​udp_ip_rx.v ​                : UDP frame receiver     rtl/​udp_ip_rx.v ​                : UDP frame receiver
     rtl/​udp_ip_rx_64.v ​             : UDP frame receiver (64 bit)     rtl/​udp_ip_rx_64.v ​             : UDP frame receiver (64 bit)
     rtl/​udp_ip_tx.v ​                : UDP frame transmitter     rtl/​udp_ip_tx.v ​                : UDP frame transmitter
     rtl/​udp_ip_tx_64.v ​             : UDP frame transmitter (64 bit)     rtl/​udp_ip_tx_64.v ​             : UDP frame transmitter (64 bit)
-    rtl/udp_demux.py                ​: UDP frame demultiplexer generator +    rtl/udp_mux.v                   : UDP frame multiplexer 
-    rtl/udp_demux_4.v               ​: 4 port UDP frame demultiplexer +    rtl/xgmii_baser_dec_64.v        : XGMII 10GBASE-R decoder 
-    rtl/udp_demux_64.py             : UDP frame demultiplexer generator (64 bit) +    rtl/xgmii_baser_enc_64.v        ​: XGMII 10GBASE-R encoder 
-    rtl/udp_demux_64_4.v            : 4 port UDP frame demultiplexer (64 bit) +    rtl/xgmii_deinterleave.v        : XGMII data/control de-interleaver 
-    rtl/udp_mux.py ​                 : UDP frame multiplexer generator +    rtl/xgmii_interleave.v          : XGMII data/control interleaver
-    rtl/udp_mux_4.v                 ​: 4 port UDP frame multiplexer +
-    rtl/udp_mux_64.py ​              : UDP frame multiplexer generator (64 bit) +
-    rtl/​udp_mux_64_4.v ​             : 4 port UDP frame multiplexer (64 bit)+
 </​code>​ </​code>​
  
Line 261: Line 457:
  
 transfer with header data transfer with header data
 +
 <​code>​ <​code>​
                   __    __    __    __    __    __    __                   __    __    __    __    __    __    __
Line 270: Line 467:
                         _____                         _____
     hdr_data ​  ​XXXXXXXXX_HDR_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX     hdr_data ​  ​XXXXXXXXX_HDR_XXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-                        ___________ _____ _____ 
-    tdata      XXXXXXXXX_A0________X_A1__X_A2__XXXXXXXXXXXX 
                         ___________ _____ _____                         ___________ _____ _____
     tdata      XXXXXXXXX_A0________X_A1__X_A2__XXXXXXXXXXXX     tdata      XXXXXXXXX_A0________X_A1__X_A2__XXXXXXXXXXXX
Line 288: Line 483:
  
 two byte transfer with sink pause after each byte two byte transfer with sink pause after each byte
 +
 <​code>​ <​code>​
               __    __    __    __    __    __    __    __    __               __    __    __    __    __    __    __    __    __
Line 307: Line 503:
  
 two back-to-back packets, no pauses two back-to-back packets, no pauses
 +
 <​code>​ <​code>​
               __    __    __    __    __    __    __    __    __               __    __    __    __    __    __    __    __    __
Line 326: Line 523:
  
 bad frame bad frame
 +
 <​code>​ <​code>​
               __    __    __    __    __    __               __    __    __    __    __    __
Line 346: Line 544:
 ===== Testing ===== ===== Testing =====
  
-Running the included testbenches requires MyHDL and Icarus Verilog. ​ Make sure that myhdl.vpi is installed properly for cosimulation to work correctly. ​ The testbenches can be run with a Python test runner like nose or py.test, or the individual test scripts can be run with python directly.+Running the included testbenches requires MyHDL and Icarus Verilog. ​ Make sure 
 +that myhdl.vpi is installed properly for cosimulation to work correctly. ​ The 
 +testbenches can be run with a Python test runner like nose or py.test, or the 
 +individual test scripts can be run with python directly.
  
 ==== Testbench Files ==== ==== Testbench Files ====
Line 353: Line 554:
     tb/​arp_ep.py ​        : MyHDL ARP frame endpoints     tb/​arp_ep.py ​        : MyHDL ARP frame endpoints
     tb/​axis_ep.py ​       : MyHDL AXI Stream endpoints     tb/​axis_ep.py ​       : MyHDL AXI Stream endpoints
 +    tb/​baser_serdes.py ​  : MyHDL 10GBASE-R SERDES endpoints
     tb/​eth_ep.py ​        : MyHDL Ethernet frame endpoints     tb/​eth_ep.py ​        : MyHDL Ethernet frame endpoints
 +    tb/​gmii_ep.py ​       : MyHDL GMII endpoints
     tb/​ip_ep.py ​         : MyHDL IP frame endpoints     tb/​ip_ep.py ​         : MyHDL IP frame endpoints
 +    tb/​mii_ep.py ​        : MyHDL MII endpoints
 +    tb/​rgmii_ep.py ​      : MyHDL RGMII endpoints
     tb/​udp_ep.py ​        : MyHDL UDP frame endpoints     tb/​udp_ep.py ​        : MyHDL UDP frame endpoints
 +    tb/​xgmii_ep.py ​      : MyHDL XGMII endpoints
 </​code>​ </​code>​
  
en/verilog/ethernet/readme.txt · Last modified: 2019/04/04 07:34 by alex
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