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en:verilog:axis:start [2014/11/09 09:24] – [Introduction] alexen:verilog:axis:start [2015/01/25 07:57] (current) – [Introduction] alex
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 Collection of AXI Stream bus components.  Most components are fully parametrizable in interface widths.  Includes full MyHDL testbench with intelligent bus cosimulation endpoints.   Collection of AXI Stream bus components.  Most components are fully parametrizable in interface widths.  Includes full MyHDL testbench with intelligent bus cosimulation endpoints.  
  
-  * AXI stream bus with adapter+  * AXI stream bus width adapter
   * AXI stream synchronous FIFO   * AXI stream synchronous FIFO
   * AXI stream asynchronous FIFO   * AXI stream asynchronous FIFO
en/verilog/axis/start.1415525066.txt.gz · Last modified: by alex
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