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| en:verilog:axis:start [2014/11/09 07:03] – created alex | en:verilog:axis:start [2015/01/25 07:57] (current) – [Introduction] alex | ||
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| Collection of AXI Stream bus components. | Collection of AXI Stream bus components. | ||
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| + | * AXI stream bus width adapter | ||
| + | * AXI stream synchronous FIFO | ||
| + | * AXI stream asynchronous FIFO | ||
| + | * AXI stream synchronous frame FIFO | ||
| + | * AXI stream asynchronous frame FIFO | ||
| + | * AXI stream/ | ||
| + | * AXI stream rate limiter | ||
| + | * AXI stream statistics collection | ||
| + | |||
| + | ===== Documentation ===== | ||
| + | |||
| + | [[readme]] | ||
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| ===== Repository ===== | ===== Repository ===== | ||