Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
en:verilog:axis:start [2014/11/09 10:24]
alex [Introduction]
en:verilog:axis:start [2015/01/25 08:57] (current)
alex [Introduction]
Line 5: Line 5:
 Collection of AXI Stream bus components. ​ Most components are fully parametrizable in interface widths. ​ Includes full MyHDL testbench with intelligent bus cosimulation endpoints.  ​ Collection of AXI Stream bus components. ​ Most components are fully parametrizable in interface widths. ​ Includes full MyHDL testbench with intelligent bus cosimulation endpoints.  ​
  
-  * AXI stream bus with adapter+  * AXI stream bus width adapter
   * AXI stream synchronous FIFO   * AXI stream synchronous FIFO
   * AXI stream asynchronous FIFO   * AXI stream asynchronous FIFO